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| - 1 - K522H1HACF-B050 rev. 1.0, oct. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2010 samsung electronics co., ltd. all rights reserved. mcp specification 2gb (128m x16) nand flash + 1gb (64m x16 ) mobile ddr sdram datasheet
- 2 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 revision history revision no. history draft date remark editor 1.0 initial issue. - 2gb nand flash w-die_ ver 1.0 - 1gb mobile ddr f-die_ ver 1.0 oct. 21, 2010 final k.n.kang - 3 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 1. features ? vdd/vddq = 1.8v/1.8v ? double-data-rate architecture; tw o d ata transfers per clock cycle. ? bidirectional data strobe (dqs). ? four banks operation. ? differential clock inputs (ck and ck ). ? mrs cycle with address key programs. ? emrs cycle with address key programs. ? internal temperature compensated self refresh. ? all inputs except data & dm are sampled at the positive going edge of the sy stem clock (ck). ? data i/o transactions on both edges of data strobe, dm for masking. ? edge aligned data output, center aligned data input. ? no dll; ck to dqs is not synchronized. ? dm for write masking only. ? auto refresh duty cycle. ? clock stop capability. - 4 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 2. general description the k522h1hacf is a multi chip package memory which combines 2g bit nand flash and 1g bit mobile ddr synchronous dynamic ram. nand cell provides the most cost-effective solution for the solid state application market. a program operation can be performe d in typical 250 p s on the (2k+64)byte page and an erase operation can be performed in typical 2m s on a (128k+4k)byte block. data in the data register can be read out at 42ns cycle time per byte. the i/o pins serve as the ports for addr ess and data input/output as well as command input. the on-chip wr ite controller automates all program and erase functions including pulse repetition, where required, and in ternal verification and margining of data. ev en the write-intensive sys- tems can take advantage of the device c s extended reliability of 100k program/e rase cycles by providing ecc(error correcting code) with real time map- ping-out algorithm. the device is an optimum solution for large nonvolatile storage applications such as solid state file stora ge and other portable applications requiri ng non-volatility. in 1gbit mobile ddr, synchronous design make a device controlled precisel y with the use of system clock. range of operating fre quencies, programma- ble burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performanc e memory system appli- cations. the k522h1hacf is suitable for use in data memory of mobile comm unication system to reduce not only mount area but also power c onsumption. this device is available in 153-ball fbga type. - 5 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3. pin configuration 153 fbga: top view (ball down) - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a dnu dnu nc vssn vccn vssqd vddqd vddqd vssqd vssd vddd vssqd dnu dnu b dnu vssn /ren clen /wpn /wen nc nc nc dq12d nc nc vddqd dnu c vssd nc /wed alen /cen r/b n dq14d dq8d dq13d nc nc dq9d udmd vddqd d vddd /csd ba0d index ------- nc nc vssqd enc /rasd a2d - vccn nc nc nc nc nc - nc dq15d udqsd f /casd a12d a0d - nc ---- nc - dq11d dq10d vssqd g cked a9d ba1d - vssn ---- nc - vddd vddqd ckd h vddd a11d a7d - io8n ---- io15n - vssd vddqd /ckd j a4d vssd a5d - io9n ---- io14n - ldqsd nc vssqd k a6d a10d a3d - io10n io11n vccn vssn io12n io13n - dq2d ldmd dq4d l a13d a8d a1d-------- dq5d dq7d vssqd m vssd vddd nc io5n io2n io0n dq6d dq3d nc nc nc nc dq0d vddqd n dnu vccn nc io6n io3n vssqd nc dq1d nc nc nc nc vddqd dnu p dnu dnu vssn io7n io4n io1n vddqd vddqd vssqd vssd vddd vssqd dnu dnu nand flash mobile dram power ground nc/dnu - 6 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 4. pin description pin name pin function(nand flash) pin name pin function(mobile ddr) io0n ~ io15n data input/output ckd, /ckd system clock & differential clock r/b n ready/busy output cked clock enable /ren read enable /csd chip select /wen write enable /rasd row address strobe alen address latch enable /casd column address strobe /wpn write protection /wed write enable /cen chip enable a0d ~ a13d address input clen command latch enable ba0d ~ ba1d bank select address vccn power supply ldmd,udmd lower / upper input data mask vssn ground ldqsd , udqsd lower / upper data strobe dq0d ~ dq15d data input/output vddd power supply pin name pin function vddqd data out power dnu do not use vssd ground nc no connected vssqd dq ground - 7 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 5. ordering information k 5 2 2h 1h a c f - b 0 50 samsung mcp memory(2chips) device type nand + mobile ddr sdram nand density,organization 2h : 2g, x16 flash block architecture c : uniform block version f : 7th generation mobile ddr speed 50 : 400mbps@cl3 operating voltage a : 1.8v / 1.8v package b : fbga(hf, osp lf) mobile ddr density, organization 1h : 1g, x16 nand speed 0 : none - 8 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 6. functional block diagram /wpn clen /wen /ren r/b n /cen io0n to io15n /csd /casd /rasd cked /wed ckd, /ckd a0d ~ a13d ldmd, udmd ba0d ~ ba1d ldqsd, udqsd alen 2gb nand flash memory dq0d to dq15d 1gb mobile ddr sdram vddd vddqd vccn vssn vssd vssqd - 9 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 7. package dimension 153-ball fine pitch ball grid arr ay package (measured in millimeters) units:millimeters 0.22 0.05 top view 153- ? 0.30 0.05 0.20 m a b ? (datum a) 1 42 765 3 8 #a1 index mark 8.00 0.10 9.00 0.10 9 10 0.50 x 13 = 6.50 0.50 x 13 = 6.50 a b c e g d f h j l k m n 3.25 bottom view p 14 13 12 11 3.25 0.50 (datum b) 0.08 max 0.90 0.10 8.00 0.10 9.00 0.10 #a1 0.25 0.50 0.25 a b - 10 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 2gb (128m x16) nand flash w-die figure 2. array organization 2k bytes 64 bytes 2k bytes 8 bit 64 bytes 1 block = 64 pages (128k + 4k) byte i/o 0 ~ i/o 7 1 page = (2k + 64)bytes 1 block = (2k + 64)byte x 64 pages = (128k + 4k) bytes 1 device = (2k+64)b x 64pages x 2,048 blocks = 2,112 mbits for 2gb page register 2,048 blocks for 2gb 4,096 blocks for 4gb ddp 1 device = (2k+64)b x 64pages x 4,096 blocks = 4,224 mbits for 4gb ddp (x8) figure 1. functional block diagram v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 12 - a 29 * a 0 - a 11 command ce re we cle wp i/0 0 i/0 7 v cc v ss ale 2,048m + 64m bit for 2gb nand flash array y-gating data register & s/a 4,096m + 128m bit for 4gb ddp (x8) - 11 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 [table 1] array address : (x8) note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than required. * a29 is row address for 4g ddp. in case of 2g mono, a29 must be set to "low" i/o i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 address 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 column address 2nd cycle a 8 a 9 a 10 a 11 *l *l *l *l column address 3rd cycle a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 row address 4th cycle a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 row address 5th cycle a 28 *a 29 *l *l *l *l *l *l row address figure 4. figure 2-2. array organization 1k words 32 words 1k words 16 bit 32 words 1 block = 64 pages (64k + 2k)word i/o 0 ~ i/o 15 1 page = (1k + 32)word 1 block = (1k + 32)word x 64 pages = (64k + 2k)words 1 device = (1k + 32)word x 64pages x 2,048 blocks = 2,112 mbits for 2gb page register 2,048 blocks for 2gb 4,096 blocks for 4gb ddp 1 device = (1k + 32)word x 64pages x 4,096 blocks = 4,224 mbits for 4gb ddp (x16) figure 3. unctional block diagram v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 11 - a 28 * a 0 - a 10 command ce re we cle wp i/0 0 i/0 15 v cc v ss ale 2,048m + 64m bit for 2gb nand flash array y-gating data register & s/a 4,096m + 128m bit for 4gb ddp (x16) - 12 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 [table 2] array address : (x16) note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than required. * a28 is row address for 4g ddp. in case of 2g mono, a28 must be set to "low" i/o i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8~i/o 15 address 1st cycle a 0 a 1 a 2 a 3 a 4 a5 a 6 a 7 *l column address 2nd cycle a 8 a 9 a 10 *l *l *l *l *l *l column address 3rd cycle a 11 a 12 a 13 a 14 a 15 a16 a 17 a 18 *l row address 4th cycle a 19 a 20 a 21 a 22 a 23 a24 a 25 a 26 *l row address 5th cycle a 27 *a 28 *l *l *l *l *l *l *l row address - 13 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 1.0 product introduction nand flash memory has addresses multiplexed into 8 i/os(x16 device case : lower 8 i/os). this scheme dram atically reduces pin c ounts and allows sys- tem upgrades to future densities by maintaining consistency in system board design. command, address and data are all written t hrough i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to mul- tiplex command and address respectively, via t he i/o pins. some commands require one bus cycle. for example, reset command, sta tus read com- mand, etc require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. page r ead and page program need the same five addres s cycles following the required command input. in block erase operation, however, only the three row address cycles are used. device operations are selected by writing specific comman ds into the command register. table 3 defines the specific commands of the device. in addition to the enhanced architecture and interface, the devic e incorporates copy-back program feature from one page to anot her page without need for transporting the data to and from the external buffer memory. since the time-consuming serial access and data-input cycles are removed, system per- formance for solid-state disk appl ication is signifi cantly increased. [table 3] command sets note : 1) random data input/output can be executed in a page. caution : any undefined command inputs are prohibited except for above command set of table 3. function 1st cycle 2nd cycle acceptable command during busy read 00h 30h read id 90h - read for copy back 00h 35h reset ffh - o page program 80h 10h copy-back program 85h 10h block erase 60h d0h random data input 1) 85h - random data output 1) 05h e0h read status 70h - o - 14 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 1.1 absolute maximum ratings note : 1) minimum dc voltage is -0.6v on input/output pins. during tran sitions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is vcc+0.3v which, during transitions, may overshoot to vcc+2.0v for periods <20ns. 2) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data shee t. exposure to absolute maximum ra ting conditions for extended per iods may affect reliability. 1.2 recommended operating conditions (voltage reference to gnd, t a =-25 to 85 q c) 1.3 dc and operating characteristics (recommended operating cond itions otherwise noted.) note : 1) v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. 2) typical value is measured at vcc=1.8v, t a =25 q c. not 100% tested. parameter symbol rating unit voltage on any pin relative to v ss v cc -0.6 to + 2.45 v v in -0.6 to + 2.45 v i/o -0.6 to vcc + 0.3 (< 2.45v) temperature under bias t bias -30 to +125 q c storage temperature t stg -65 to +150 q c short circuit current i os 5ma parameter symbol min typ. max unit supply voltage v cc 1.7 1.8 1.95 v supply voltage v ss 000v parameter symbol test conditions min typ max unit operating current page read with serial access i cc1 t rc =42ns ce =v il , i out =0ma - 15 25 ma program i cc2 -- erase i cc3 -- stand-by current(ttl) i sb1 2gb,ce =v ih , wp =0v/v cc --1 4gb ddp,ce =v ih , wp =0v/v cc --2 stand-by current(cmos) i sb2 2gb,ce =v cc -0.2, wp =0v/v cc -1050 p a 4gb ddp,ce =v cc -0.2, wp =0v/v cc - 20 100 input leakage current i li v in =0 to v cc (max) - - 10 output leakage current i lo v out =0 to v cc (max) - - 10 input high voltage v ih 1) - 0.8xv cc - v cc +0.3 v input low voltage, all inputs v il 1) - -0.3 - 0.2xvcc output high voltage level v oh i oh =-100 p av cc -0.1 -- output low voltage level v ol i ol =100ua --0.1 output low current(r/b ) i ol (r/b )v ol =0.1v 34-ma - 15 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 1.4 valid block note : 1) the device may include initial invalid blocks when first ship ped. additional invalid blocks may develop while being used. th e number of valid blocks is presented with both cases of invalid blocks considered . invalid blocks are defined as bl ocks that contain one or more bad bits. do not erase or pro gram factory-marked b ad blocks. refer to the attached technical notes for appropriate management of invalid blocks. 2) the 1st block, which is placed on 00h block address, is guar anteed to be a valid block up to 1k program/erase cycles with x 8 : 1bit/ 512byte, x16 : 1bit/256word ecc. 3) each mono chip in th device has maximum 40 invalid blocks. 1.5 ac test condition (ta=-25 to 85 q c, vcc=1.7v~1.95v unless otherwise noted) 1.6 capacitance (ta=25 c, vcc=1.8v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. 1.7 mode selection note : 1) x can be vil or vih. 2) wp should be biased to cmos high or cmos low for standby. parameter symbol min typ. max unit 2gb n vb 2,008 - 2,048 blocks 4gb ddp n vb 4,016 - 4,096 blocks parameter value input pulse levels 0v to v cc input rise and fall times 5ns input and output timing levels vcc/2 output load 1 ttl gate and cl=30pf item symbol test condition min max unit input/output capacitance (mono) c i/o v il =0v -10pf input capacitance (mono) c in v in =0v -10pf input/output capacitance (ddp) c i/o v il =0v -20pf input capacitance (ddp) c in v in =0v -20pf cle ale ce we re wp mode hll hx read mode command input l h l h x address input(5clock) hll hh write mode command input l h l h h address input(5clock) l l l h h data input lllh x data output x x x x h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect xxhxx 0v/v cc 2) stand-by - 16 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 1.8 read / program / erase characteristics note : 1) typical program time is defined as the time within which mo re than 50% of the whole pages are programmed at 1.8v vcc and 25 q c temperature. 1.9 ac timing characteristics for command / address / data input note : 1) the transition of the corresponding c ontrol pins must occur only once while we is held low 2) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle parameter symbol min typ max unit read time (data transfer from cell to register) t r --40 p s program time t prog - 250 750 p s number of partial program cycles in the same page nop - - 4 cycles block erase time t bers -210ms parameter symbol min max unit cle setup time t cls 1) 21 - ns cle hold time t clh 5-ns ce setup time t cs 1) 21 - ns ce hold time t ch 5-ns we pulse width t wp 21 - ns ale setup time t als 1) 21 - ns ale hold time t alh 5-ns data setup time t ds 1) 20 - ns data hold time tdh 5-ns write cycle time t wc 40 - ns we high hold time t wh 10 - ns address to data loading time t adl 2) 100 - ns - 17 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 1.10 ac characteristics for operation note : 1) if reset command(ffh) is written at ready state, the device goes into busy for maximum 5 p s. parameter symbol min max unit ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 21 - ns we high to busy t wb - 100 ns wp low to we low (disable mode) t ww 100 - ns wp high to we low (enable mode) read cycle time t rc 42 - ns re access time t rea -30ns ce access time t cea -35ns re high to output hi-z t rhz - 100 ns ce high to output hi-z t chz -30ns ce high to ale or cle don?t care t csd 0-ns re high to output hold t roh 15 - ns ce high to output hold t coh 15 - ns re high hold time t reh 10 - ns output hi-z to re low t ir 0-ns re high to we low t rhw 100 - ns we high to re low t whr 60 - ns device resetting time(read/program/erase) t rst - 5/10/500 (1) p s - 18 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 2.0 nand flash technical notes 2.1 initial invalid block(s) figure 5. flow chart to create initial invalid block table initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is called the initial inva lid block information. devices with initial invalid block(s) h ave the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a sele ct transistor. the system design must be able to mask out the initial invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1k program/erase cycles with x8:1bit/ 512byte, x16:1bit/256word ecc. 2.2 identifying initial invalid block(s) all device locations are erased(ffh) except locations where the in itial invalid block(s) informat ion is written prior to shipping. the initial invalid block(s) status is defined by the 1st byte(1st word) in the spare area. samsung makes sure that either the 1st or 2nd page of every init ial invalid block has non-ffh data at the column address of 2048(x16:1024). since the initial inva lid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the fo llowing suggested flow chart(fi gure 5). any intentional erasur e of the original initial invalid block information is prohibited. * check "ffh(x16:ffffh)" at the start set block address = 0 check increment block address last block ? end no yes yes create (or update) no initial of the 1st and 2nd page in the block invalid block(s) table "ffh(x16:ffffh)" column address 2048(x16:1024) - 19 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 nand flash technical notes (continued) 2.3 error in write or read operation within its life time, additional invalid bl ocks may develop with nand flash memory. refer to the qualification report for the a ctual data. block replacement should be done upon erase or program error. ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection note : a repetitive page read operation on the same block without erase ma y cause bit errors, which could be accumulated over time an d exceed the coverage of ecc. soft- ware scheme such as caching into ram is recommended. program flow chart failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read up to 1 bit-failure verity ecc -> ecc correction start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * - 20 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 nand flash technical notes (continued) block replacement * step1 when an error happens in the nth page of the bloc k ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program to block ?a? by creating an ?invalid block? table or other appropriate scheme. erase flow chart read flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes write 30h buffer memory of the controller. 1st block a block b (n-1)th nth (page) ^ a 1st (n-1)th nth (page) ^ a an error occurs. 1 2 - 21 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 nand flash technical notes (continued) 2.4 addressing for program operation within a block, the pages must be programmed consecutively from the lsb(l east significant bit) page of the block to the msb(mos t significant bit) pages of the block. random page address programming is prohibited. in th is case, the definition of lsb page is the lsb among the page s to be programmed. therefore, lsb doesn't need to be page 0. from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 : : : : figure 7. read operation with ce don?t-care. figure 6. program operation with ce don?t-care. - 22 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 2.5 system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or serial access as shown below. the internal 2,112byte data registers are uti- lized as separate buffers for this operation and the system de sign gets more flexible. in addition, for voice or audio applicat ions which use sl ow cycle time on the order of - 23 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 note : device i/o data address i/ox data in/out col. add1 col. add2 row add1 row add2 row add3 2gb(x8) i/o 0 ~ i/o 7 ~2,112byte a0~a7 a8~a11 a12~a19 a20~a27 a28 4gb ddp(x8) i/o 0 ~ i/o 7 ~4,224byte a0~a7 a8~a11 a12~a19 a20~a27 a28~a29 2gb(x16) i/o 0 ~ i/o 15 ~1,056word a0~a7 a8~a10 a11~a18 a19~a26 a27 4gb ddp(x16) i/o 0 ~ i/o 15 ~2,112word a0~a7 a8~a10 a11~a18 a19~a26 a27~a28 - 24 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.0 timing diagrams 3.1 command latch cycle ce we cle ale command t cls t cs t clh t ch t wp t als t alh t ds t dh i/ox 3.2 address latch cycle ce we cle ale col. add1 t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t dh t alh t als t wh t ds t dh t wp i/ox col. add2 row add1 row add2 t wc t wh t alh t als t ds t dh row add3 t alh t cls t ds - 25 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.3 input data latch cycle ce cle we din 0 din 1 din final ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp - 26 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.5 ce we cle re 70h status output t clr t clh t wp t ch t ds t dh t rea t ir t rhoh t coh t whr t cea t cls i/ox t chz t rhz t cs status read cycle 3.6 read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc - 27 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.7 read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h i/ox col. add1 col. add2 row add1 row add2 row add3 t coh t clr t csd - 28 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.8 random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t w b t ar t r t rr 30h 05h column address dout m dout m+1 i/ox col. add1 col. add2 row add1 row add2 col add1 col add2 row add3 t clr e0h t whr t rea t rc t rhw - 29 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.9 page program operation ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc - 30 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.10 page program operation with random data input ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc - 31 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.11 copy-back program operation with random data input 00h i/o x 85h column address row address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc - 32 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.12 block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc - 33 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.13 read id operation ce cle we ale re 90h read id command maker code device code 00h ech t rea address 1cycle i/ox t ar device 4th cyc. code 3rd cyc. 5th cyc. 3.13.1. id definition table 90 id : access command = 90h device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle 2gb(x8) aah 00h 15h 44h 4gb ddp(x8) ach 01h 15h 48h 2gb(x16) bah 00h 55h 44h 4gb ddp(x16) bch 01h 55h 48h description 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte maker code device code internal chip number page size, block size,red undant area size, organization plane number, plane size, ecc level - 34 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3rd id data 4th id data item description i/o # 7 6 5 4 3 2 1 0 internal chip number 1 2 4 8 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 number of simultaneously programmed pages 1 2 4 8 0 0 1 1 0 1 0 1 interleave program between multii-chips not supported supported 0 1 cache program not supported supported 0 1 item description i/o # 7 6 5 4 3 2 1 0 page size (without redundant area) 1kb 2kb 4kb 8kb 0 0 1 1 0 1 0 1 block size (without redundant area) 64kb 128kb 256kb 512kb 0 0 1 1 0 1 0 1 redundant area size (byte/512byte) 8 16 reserved reserved 0 0 1 1 0 1 0 1 organization x8 x16 0 1 reserved 0 or 1 - 35 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 5th id data item description i/o # 7 6 5 4 3 2 1 0 ecc level 1bit ecc/512byte 2bit ecc/512byte 4bit ecc/512byte reserved 0 0 1 1 0 1 0 1 plane number 1 2 4 8 0 0 1 1 0 1 0 1 plane size (without redundant area) 64kb 128kb 256kb 512kb 1gb 2gb 4gb 8gb 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 reseved reserved 0 - 36 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 4.0 device operation figure 8. read operation address(5cycle) 00h col. add.1,2 & row add.1,2,3 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox figure 10. random data input in a page 80h r/b address & data input i/o0 pass 10h 70h fail t prog 85h address & data input i/ox col. add.1,2 & row add1,2,3 col. add.1,2 data data "0" "1" figure 9. program & read status operation 80h r/b address & data input i/o0 pass data 10h 70h fail t prog i/ox col. add.1,2 & row add.1,2,3 "0" "1" - 37 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 4.2 page program the device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte(a word) or co nsecutive byte up to 2,112 bytes(1,056 words), in a single page program cycle. the number of consecutive partial page programming operation within t he same page without an intervening erase operation must not exceed 4 times for a si ngle page. the addressing should be done in sequential order in a block. a page program cycle consists of a serial data loading pe riod in which up to 2,112 bytes(1,056 words) of data may be loaded into the data regi ster, followed by a non-vol- atile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input command(80h) , followed by the fi ve cycle address input s and then serial data loading. the bytes(words) other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). r andom data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming pr ocess. writing 10h alone without previously entering the seri al data will not initiate the programming process. the internal write state controller aut omatically executes the algorit hms and timings necessary for pr ogram and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status reg- ister. the system controller can detect the comp letion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programmi ng is in progress. when the page program is complete, the wr ite status bit(i/ o 0) may be checked(figure 9). the internal write verify detects only errors for "1"s that are not successfully programmed to " 0"s. the command register remains in read status command mode until another valid command is written to the command register. figure 12. page copy-back program operation with random data input figure 11. page copy-back program operation - 38 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 4.3 copy-back program copy-back program with read for copy-back is configured to quick ly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. since the ti me-consuming re-loading cycles are removed, the system performance is improved. the be nefit is especially obvi- ous when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. co py-back operation is a sequential execution of read for copy-back and of copy-back program with the destination page address. a read operation with "3 5h" command and the address of the source page moves the whole 2,112 bytes(1,056 words) data into the internal data buffer. a bit error is checked by sequential reading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore copy-back program operatio n is initiated by issuing page-copy data-input command (85h) with destination page address. actual programming operation begins after program confirm com mand (10h) is issued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the stat us register. when the copy-back program is complete, the write status bit(i/o 0) may be checked(figure 11 & figure 12). the command register remains in read status comma nd mode until another valid command is written to the command register. during copy-back program, data modificati on is possible using random data input command (85h) as shown in figure 12. note : 1) copy-back program operation is allowed only within the same memory plane. "0" "1" 00h r/b add.(5cycles) i/o0 pass fail t prog t r source address destination address i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 35h data output 85h add.(5cycles) 10h 70h figure 13. block erase operation 60h row add 1,2,3 r/b address input(3cycle) i/o0 pass d0h 70h fail t bers i/ox "0" "1" - 39 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 4.4 block erase the erase operation is done on a block basis. block address loading is acco mplished in three cycles initiated by an erase setup command(60h). only block address is valid while page address is ignored. the eras e confirm command(d0h) followi ng the block address loading initia tes the internal erasing process. this two-step sequence of setup followed by executi on command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write cont roller handles erase and erase- verify. when the erase operation is completed, the write status bit(i/o 0) ma y be checked. figure 13 details the sequence. 4.5 read status the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle outputs the content of the status register to the i/ o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple mem- ory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status . refer to table 4 for specific status register definitions. the command register remains in status r ead mode until further commands are issued to it. therefore, if t he status register is read during a random read cycle, the read command(00h) should be given befor e starting read cycles. [table 4] status register definition for 70h command note : 1) i/os defined ?not use? are recommended to be masked out when read st atus is being executed. 4.6 read id the device contains a product identificati on mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. five read cycles sequentially output the manufacturer code(ech), and the device code and 3rd, 4th, 5th cycle id respectively. the command regis ter remains in read id mode until further commands are issued to it. figure 14 shows the operation sequence. i/o page program block erase read definition i/o 0 pass/fail pass/fail not use pass : "0" fail : "1" i/o 1 not use not use not use don?t -cared i/o 2 not use not use not use don?t -cared i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect protected : "0" not protected : "1" figure 14. read id operation ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea t whr t clr device 4th cyc. code ech 3rd cyc. 5th cyc. figure 15. reset operation ffh i/o x r/b t rst - 40 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 4.7 reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait fo r the next command, and the status register is cleared to value c0h when wp is high. if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin changes to low for trst after the reset command is written. refer to figure 15 below. [table 5] device status device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle 2gb(x8) aah 00h 15h 44h 4gb ddp(x8) ach 01h 15h 48h 2gb(x16) bah 00h 55h 44h 4gb ddp(x16) bch 01h 55h 48h after power-up after reset operation mode mode 00h command is latched waiting for next command figure 16. rp vs tr ,tf & rp vs ibusy - 41 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 4.8 ready/ busy the device has a r/b output that provides a hardware method of indicating the comp letion of a page program, erase and random read completion. the r / b pin is normally high but transit ions to low after program or erase command is written to the command register or random read i s started after address loading. it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby al lowing two or more r/b outputs to be or-tied. because pull-up resi stor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the fol- lowing reference chart(fig.17). its valu e can be determined by the following guidance. rp value guidance where i l is the sum of the input currents of all devices tied to the r/b pin. rp(max) is determined by maxi mum permissible limit of tr v cc r/b open drain output device gnd rp ibusy busy ready vcc voh tf tr vol 1.8v device - v ol : 0.1v, v oh : v cc -0.1v c l vcc tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 figure 17. ac waveforms for power transition - 42 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 5.0 data protection & power up sequence the device is designed to offer pr otection from any involuntary program/erase du ring power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 1.1v. wp pin provides hardware protecti on and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 100 figure 19. erase operation 1. enable mode 60h d0h we i/o wp r/b tww(min.100ns) 2. disable mode 60h d0h we i/o wp r/b tww(min.100ns) datasheet mcp memory rev. 1.0 5.1 wp ac timing guide enabling wp during erase and program busy is prohibited. the erase and program operations ar e enabled and disabled as follows: - 4 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 1gb (64m x16 ) mobile ddr sdram - 5 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 1.0 functional block diagram bank select ti ming register dm input register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 6mx32 6mx32 6mx32 6mx32 sense amp 2-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ck, ck add lcke ck, ck cke cs ras cas we lcas lras lcbr lwe lwcbr lras lcbr ck, ck 32 32 16 16 ldm x16 dqi data strobe dm ldm lwe figure 1. state diagram - 6 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 2.0 functional description read self refresh auto refresh power down row active reada writea writea precharge preall idle power down refs refsx refa mrs ckel ckeh act ckeh ckel write write writea reada pre pre reada reada read read automatic sequence command sequence writea burst stop self refresh partial pre mrs emrs all banks precharge on power power applied all banks precharged pre - 7 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.0 mode register definition figure 2. mode register set 3.1 mode register set (mrs) the mode register is designed to support the va rious operating modes of mobile ddr sdra m. it includes cas latency, addressing m ode, burst length, test mode and vendor specific options to make mobile ddr sdram us eful for variety of applications . the mode register is written by asserting low on cs , ras , cas and we (the mobile ddr sdram should be in active mode with cke already high prior to writi ng into the mode register). the states of address pins a0 ~ a13 and ba0, ba1 in the same cycle as cs , ras , cas and we going low are written in the mode register. two clock cycles are required to complete the write operation in the mode register. even if the power-up sequence is finished and some read or write operation is executed afterward, the mode register contents can be changed with the sa me command and two clock cycles. this command must be issued on ly when all banks are in the idle state. the mode register is divided into variou s fields depending on functionality. the burst length uses a0 ~ a2, addressing mode uses a3, cas latency (read latency from column address) uses a4 ~ a6, a7 ~ a13 is used for test mode. ba0 and ba1 must be set to low for proper mrs opera- tion. note : 1) rfu (reserved for future use) should stay "0" during mrs cycle . address bus a 2 a 1 a 0 burst type 0 0 0 reserved 001 2 010 4 011 8 100 16 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved a 3 burst type 0 sequential 1 interleave mode register ba1 ba0 a13 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 bt burst length 0 r f u 1) 0 0 0 cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 011 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved - 8 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 [table 1] burst address ordering for burst length burst length starting address (a3, a2, a1, a0) sequential mode interleave mode 2 xxx0 0, 1 0, 1 xxx1 1, 0 1, 0 4 xx00 0, 1, 2, 3 0, 1, 2, 3 xx01 1, 2, 3, 0 1, 0, 3, 2 xx10 2, 3, 0, 1 2, 3, 0, 1 xx11 3, 0, 1, 2 3, 2, 1, 0 8 x000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 x001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 x010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 x011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 x100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 x101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 x110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 x111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 16 0000 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 0001 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14 0010 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1 2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13 0011 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12 0100 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11 0101 5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10 0110 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9 0111 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8 1000 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7 8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7 1001 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8 9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6 1010 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5 1011 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4 1100 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3 1101 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12 13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2 1110 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1 1111 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 figure 3. extended mode register set - 9 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.2 extended mode register set (emrs) the extended mode register is designed to support for the desired operating modes of ddr sdram. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba1, low on ba0(the mobile ddr sdram should be in al l bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a0 ~ a13 in the same cycle as cs , ras , cas and we going low is written in the extended mode register. two clock cycles are required to complete the write operation in the extended mode register. even if the power-u p sequence is finished and some read or write operations is executed afterward, the m ode register contents can be changed with the same command and tw o clock cycles. but this command must be issued only when all banks ar e in the idle state. a0 - a2 are used for partial array self refresh and a5 - a7 are used for driver strength control. "high" on ba1 and "low" on ba0 are used for em rs. all the other address pins ex cept a0,a1,a2,a5,a6,a7, ba1, ba0 must be set to low for proper emrs operation. refer to the table for specific codes. note : 1) rfu (reserved for future use) should stay "0" during emrs cycle. address bus ba1 ba0 a13 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 1 pasr 0 rfu 1) 0 0 rfu 1) ds a 7 a 6 a 5 driver strength 000 full 001 1/2 010 1/4 011 1/8 100 3/4 101 3/8 110 5/8 111 7/8 pasr a 2 a 1 a 0 refreshed area 0 0 0 full array 0 0 1 1/2 array 0 1 0 1/4 array 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved ds - 10 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3.3 internal temperature compensated self refresh (tcsr) figure 4. emrs code and tcsr, pasr 1. in order to save power consumption, this mobile dram incl udes th e internal temperature sensor and control units to control t he self refresh cycle auto- matically according to the real device temperature. 2. tcsr ranges for idd6 shown in the table are only examples. 3. if the emrs for external tcsr is issued by th e controller, this emrs code for tcsr is ignored. note : 1) idd6 85 - 11 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 4.0 absolute maximum ratings note : 1) permanent device damage may occur if absolute maximum ratings are exceeded. 2) functional operation should be restricted to recommend operation condition. 3) exposure to higher than recommended voltage for exte nded periods of time could affect device reliability. 5.0 dc operating conditions recommended operating conditions (voltage referenced to vss=0v, t c = -25 q c to 85 q c) note : 1) under all conditions, vddq must be less than or equal to vdd. 2) these parameters should be tested at th e pin on actual components and may be checked at either the pin or the pad in simulat ion. 3) any input 0v d vin d vddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. parameter symbol value unit voltage on any pin relative to vss v in , v out - 0.5 ~ 2.7 v voltage on vdd supply relative to vss vdd - 0.5 ~ 2.7 v voltage on vddq supply relative to vss vddq - 0.5 ~ 2.7 v storage temperature t stg - 55 ~ + 150 q c power dissipation p d 1.0 w short circuit current i os 50 ma parameter symbol min max unit note supply voltage (for device with a nominal vdd of 1.8v) vdd 1.7 1.95 v 1 i/o supply voltage vddq 1.7 1.95 v 1 input logic high voltage address v ih (dc) 0.8 x vddq vddq + 0.3 v 2 data 0.7 x vddq vddq + 0.3 v input logic low voltage address v il (dc) -0.3 0.2 x vddq v 2 data -0.3 0.3 x vddq v output logic high voltage v oh (dc) 0.9 x vddq - v i oh = - 0.1ma output logic low voltage v ol (dc) - 0.1 x vddq v i ol = 0.1ma input leakage current i i -2 2 ua 3 output leakage current i oz -5 5 ua - 12 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 6.0 dc characteristics recommended operating conditions (voltage referenced to vss = 0v, t c = -25 to 85 q c) note : 1) idd5 is measured in the below test condition. 2) idd specifications are tested afte r the device is properly initialized. 3) input slew rate is 1v/ns. 4) definitions for idd: low is defined as v in d 0.1 * vddq; high is defined as v in t 0.9 * vddq; stable is defined as inputs stable at a high or low level; switching is defined as: - address and command: inputs changing between high and low once p er two clock cycles; - data bus inputs: dq changing between high an d low once per clock cycle; dm and dqs are stable. 5) idd6 85 q c is guaranteed, idd6 45 q c is typical value. parameter symbol test condition ddr400 unit note operating current (one bank active) idd0 trc=trcmin; tck=tckmin; cke is high; cs is high between valid commands; address inputs are switching; data bus inputs are stable 60 ma precharge standby current in power-down mode idd2p all banks idle, cke is low; cs is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 0.5 ma idd2ps all banks idle, cke is low; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 0.5 precharge standby current in non power-down mode idd2n all banks idle, cke is high; cs is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 8 ma idd2ns all banks idle, cke is high; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 4 active standby current in power-down mode idd3p one bank active, cke is low; cs is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 5 ma idd3ps one bank active, cke is low; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 4 active standby current in non power-down mode (one bank active) idd3n one bank active, cke is high; cs is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 12 ma idd3ns one bank active, cke is high; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 10 operating current (burst mode) idd4r one bank active; bl=4; cl=3; tck = tckmin; continuous read bursts; i out =0 ma address inputs are switching; 50% data change each burst transfer 70 ma idd4w one bank active; bl = 4; tck = tckmin; continuous write bursts; address inputs are switching; 50% data change each burst transfer 50 refresh current idd5 trc t trfc; tck = tckmin; burst refresh; cke is high; address and control inputs are switching; data bus inputs are stable 70 ma 1 self refresh current idd6 cke is low; t ck = t ckmin; extended mode register set to all 0?s; address and control inputs are stable; data bus inputs are stable tcsr range values full array 85 q c 900 ua 5 45 q c 200 1/2 array 85 q c 800 ua 45 q c 150 1/4 array 85 q c 700 ua 45 q c 120 density 128mb 256mb 512mb 1gb 2gb unit t rfc 80 80 110 140 140 ns - 13 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 7.0 ac operating conditions & timming specification note : 1) these parameters should be tested at th e pin on actual components and may be checked at either the pin or the pad in simulat ion. 2) the value of v ix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. parameter/condition symbol min max unit note input high (logic 1) voltage, all inputs v ih (ac) 0.8 x vddq vddq + 0.3 v 1 input low (logic 0) voltage, all inputs v il (ac) -0.3 0.2 x vddq v 1 input crossing point voltage, ck and ck inputs v ix (ac) 0.4 x vddq 0.6 x vddq v 2 - 14 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 8.0 ac timming parameters & specifications parameter symbol ddr400 unit note min max clock cycle time cl=3 t ck 5 ns 1,2 row cycle time t rc 55 ns row active time t ras 40 70,000 ns ras to cas delay t rcd 15 ns row precharge time t rp 15 ns row active to row active delay t rrd 10 ns write recovery time t wr 12 ns last data in to active delay t dal - - 3 last data in to read command t cdlr 2 tck col. address to col. address delay t ccd 1 tck clock high level width t ch 0.45 0.55 tck clock low level width t cl 0.45 0.55 tck dq output data access time from ck / ck cl=3 t ac 2 5 ns 4 dqs output data access time cl=3 t dqsck 2 5 ns data strobe edge to output data edge t dqsq 0.4 ns read preamble cl=3 t rpre 0.9 1.1 tck read postamble t rpst 0.4 0.6 tck ck to valid dqs-in t dqss 0.75 1.25 tck dqs-in setup time t wpres 0 ns 5 dqs-in hold time t wpreh 0.25 tck dqs-in high level width t dqsh 0.4 0.6 tck dqs-in low level width t dqsl 0.4 0.6 tck dqs falling edge to ck setup time t dss 0.2 tck dqs falling edge hold time from ck t dsh 0.2 tck dqs-in cycle time t dsc 0.9 1.1 tck address and control input setup time fast slew rate t is 0.9 ns 7 slow slew rate 1.1 8 address and control input hold time fast slew rate t ih 0.9 ns 7 slow slew rate 1.1 8 address & control input pulse width t ipw 2.2 dq & dm setup time to dqs fast slew rate t ds 0.48 ns 6,7 slow slew rate 0.58 6,8 dq & dm hold time to dqs fast slew rate t dh 0.48 ns 6,7 slow slew rate 0.58 6,8 dq & dm input pulse width t dipw 1.2 ns dq & dqs low-impedence time from ck / ck t lz 1.0 ns dq & dqs high-impedence time from ck / ck t hz 5 ns dqs write postamble time t wpst 0.4 0.6 tck - 15 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 note : 1) t ck (max) value is measured at 100ns. 2) the only time that the clock frequency is allowed to be changed is during clock stop, power-down, self-refresh modes. 3) in case of below 33mhz (t ck =30ns) condition, sec could support t dal (=2*tck). t dal =(t wr /t ck ) + (t rp /t ck ) 4) t ac (min) value is measured at the high vdd (1.95v) and cold temperature (-25 q c). t ac (max) value is measured at the low vdd (1.7v) and hot temperature (85 q c). t ac is measured in the device with half driver strength and under the ac output load condition (fig.6 in next page). 5) the specific requirement is that dqs be valid (high or low) on or before this ck edge. the case shown (dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depend ing on t dqss . 6) i/o delta rise/fall ra te(1/slew-rate) derating this derating table is used to increase t ds /t dh in the case where the dq and dqs slew rates differ. the delta rise/fall rate is calculated as 1/slewrate1-1/slewrate2. for example, if slew rate 1 = 1.0v/ns and slew rate 2 =0.8v/ns, then the delta rise/fall rate =-0.25ns/v. 7) input slew rate 1.0 v/ ns. 8) input slew rate 0.5v/ns and < 1.0v/ns. 9) maximum burst refresh cycle : 8 parameter symbol ddr400 unit note min max dqs write preamble time t wpre 0.25 tck refresh interval time t ref 64 ms mode register set cycle time t mrd 2 tck power down exit time t pdex 2 tck cke min. pulse width (high and low pulse width) t cke 2tck auto refresh cycle time t rfc 80 ns 9 exit self refresh to active command t xsr 120 ns data hold from dqs to earliest dq edge t qh t hp min - t qhs ns data hold skew factor t qhs 0.5 ns clock half period t hp t cl min or t ch min ns data rise/fall rate ' tds ' tdh (ns/v) (ps) (ps) 000 r 0.25 +50 +50 r 0.5 +100 +100 figure 6. ac output load circuit 1), 2) figure 5. dc output load circuit - 16 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 9.0 ac operating test conditions (vdd = 1. 7 v to 1.95 v, tc = -25 - 17 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 10.0 input/output capacitance (vdd=1.8, vddq=1.8v, tc = 25 c, f=100mhz) parameter symbol min max unit input capacitance (a0 ~ a13, ba0 ~ ba1, cke, cs , ras ,cas , we ) cin1 1.5 3.0 pf input capacitance (ck, ck ) cin2 1.5 3.5 pf data & dqs input/output capacitance cout 2.0 4.5 pf input capacitance (dm) cin3 2.0 4.5 pf figure 7. ac overshoot and undershoot definition for address and control pins figure 8. ac overshoot and undershoot definition for clk, dq, dqs and dm pins - 18 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 11.0 ac overshoot/undershoot specification for address & control pins 12.0 ac overshoot/undershoot specification for clk, dq, dqs and dm pins parameter specification maximum peak amplitude allowed for overshoot area 0.9v maximum peak amplitude allowed for undershoot area 0.9v maximum overshoot area above vdd 3v-ns maximum undershoot area below vss 3v-ns parameter specification maximum peak amplitude allowed for overshoot area 0.9v maximum peak amplitude allowed for undershoot area 0.9v maximum overshoot area above vddq 3v-ns maximum undershoot area below vssq 3v-ns overshoot area maximum amplitude vdd undershoot area maximum amplitude vss volts (v) time (ns) overshoot area maximum amplitude vddq undershoot area maximum amplitude vssq volts (v) time (ns) - 19 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 13.0 command truth table (v=valid, x=don?t care, h=logic high, l=logic low) note : 1) op code : operand code. a0 ~ a13 & ba0 ~ ba1 : program keys. (@emrs/mrs) 2) emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3) auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4) ba0 ~ ba1 : bank select addresses. 5) if a10/ap is "high" at row precharge, ba0 and ba1 are ignored and all banks are selected. 6) during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7) burst stop command is valid at every burst length. 8) dm sampled at the rising and falling edges of the dqs and data -in are masked at the both edges (write dm latency is 0). 9) this combination is not defined for any function, which means "no operation(nop)" in mobile ddr sdram. command cken-1 cken cs ras cas we ba0,1 a10/ap a13~11, a9~a0 note register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll lh x 3 self refresh entry l 3 exit l h lh hh x 3 hx x x 3 bank active & row addr. h x l l h h v row address read & column address auto precharge disable hxlhlhv l column address (a0~a9) 4 auto precharge enable h4 write & column address auto precharge disable hxlhllv l column address (a0~a9) 4 auto precharge enable h4, 6 deep power down entry h l l h h l x exit l h h x x x burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lh hh exit l h x x x x precharge power down entry h l hx x x x lh hh exit l h hx x x lh hh dm h x x 8 no operation (nop) : not defined h x hx x x x 9 lh hh 9 - 20 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 14.0 functional truth table current state cs ras cas we address command action precharge standby l h h l x burst stop illegal 2) l h l x ba, ca, a10 read/write illegal 2) l l h h ba, ra active bank active, latch ra l l h l ba, a10 pre/prea illegal 4) lllh x refresh auto-refresh 5) llllop-code, m ode-add mrs mode register set 5) active standby l h h l x burst stop nop l h l h ba, ca, a10 read/reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write/writea begin write, latch ca, determine auto-precharge l l h h ba, ra active bank active/illegal 2) llhl ba, a10 pre/prea precharge/precharge all l l l h x refresh illegal llllop-code, m ode-add mrs illegal read l h h l x burst stop terminate burst l h l h ba, ca, a10 read/reada terminate burst, latch ca, begin new read, determine auto-precharge 3) l h l l ba, ca, a10 write/writea illegal l l h h ba, ra active bank active/illegal 2) l l h l ba, a10 pre/prea terminate burst, precharge 10) l l l h x refresh illegal llllop-code, m ode-add mrs illegal write l h h l x burst stop illegal l h l h ba, ca, a10 read/reada terminate burst with dm=high, latch ca, begin read, determine auto-pre- charge 3) l h l l ba, ca, a10 write/writea terminate burst, latch ca, begin new write, determine auto-pre- charge 3) l l h h ba, ra active bank active/illegal 2) l l h l ba, a10 pre/prea terminate burst with dm=high, precharge 10) l l l h x refresh illegal llllop-code, m ode-add mrs illegal read with auto precharge 6) (reada) l h h l x burst stop illegal l h l h ba, ca, a10 read/reada note6 l h l l ba, ca, a10 write/writea illegal l l h h ba, ra active note6 llhl ba, a10 pre/prea note6 l l l h x refresh illegal llllop-code, m ode-add mrs illegal - 21 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 current state cs ras cas we address command action write with auto recharge 7) (writea) l h h l x burst stop illegal l h l h ba, ca, a10 read/reada note7 l h l l ba, ca, a10 write/writea note7 l l h h ba, ra active note7 l l h l ba, a10 pre/prea note7 l l l h x refresh illegal llllop-c ode, mode-add mrs illegal precharging (during t rp ) lhhl x burst stop illegal 2) l h l x ba, ca, a10 read/write illegal 2) l l h h ba, ra active illegal 2) l l h l ba, a10 pre/prea nop 4) (idle after t rp ) l l l h x refresh illegal llllop-c ode, mode-add mrs illegal row activating (from row active to t rcd ) lhhl x burst stop illegal 2) l h l x ba, ca, a10 read/write illegal 2) l l h h ba, ra active illegal 2) l l h l ba, a10 pre/prea illegal 2) l l l h x refresh illegal llllop-c ode, mode-add mrs illegal write recovering (during t wr or t cdlr ) lhhl x burst stop illegal 2) l h l h ba, ca, a10 read illegal 2) l h l l ba, ca, a10 write write l l h h ba, ra active illegal 2) l l h l ba, a10 pre/prea illegal 2) l l l h x refresh illegal llllop-c ode, mode-add mrs illegal re- freshing l h h l x burst stop illegal l h l x ba, ca, a10 read/write illegal l l h h ba, ra active illegal l l h l ba, a10 pre/prea illegal l l l h x refresh illegal llllop-c ode, mode-add mrs illegal mode register setting l h h l x burst stop illegal l h l x ba, ca, a10 read/write illegal l l h h ba, ra active illegal l l h l ba, a10 pre/prea illegal l l l h x refresh illegal llllop-c ode, mode-add mrs illegal - 22 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 (h=high level, l=low level, x=don c t care) note : 1) all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2) illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. (illegal = device operation and/or data integrity are not guaranteed.) 3) must satisfy bus contention, bus turn around and write recovery requirements. 4) nop to bank precharging or in idle sate. may precharge bank indicated by ba. 5) illegal if any bank is not idle. 6) refer to "read with auto precharge timing diagram" for detailed information. 7) refer to "write with auto precharge timing diagram" for detailed information. 8) cke low to high transition will re-enable ck, ck and other inputs asynchronously. a minimum setup time must be satisfied before issuing any command other than exit. 9) power-down, self-refresh can be entered only from all bank idle state. current state cke n-1 cke n cs ras cas we add action self- refreshing 8) l h h x x x x exit self-refresh l h l h h h x exit self-refresh l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down l h x x x x x exit power down (idle after t pdex ) l l x x x x x nop (maintain power down) all banks idle 9) h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x enter deep power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state = power down - 1 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 mobile ddr sdram device operation & timing diagram - 2 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 device operations - 3 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 1. precharge the precharge command is used to precharge or close a bank that has been activated. the precharge command is issued when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank respectively or all banks si multane- ously. the bank select addresses(ba0, ba1) are used to define which bank is precharged when the command is initiated. for write cycle, twr(min.) must be satisfied until the precharge command can be issued. after trp from the precharge, an active command to the same bank can be initiated. [table 1] bank selection for precharge by bank address bits 2. no operation(nop) & device deselect the device should be deselec ted by deactivating the cs signal. in this mode, mobile ddr sdram shoul d ignore all the control inputs. the mobile ddr sdram is put in nop mode when cs is activated and ras , cas and we are deactivated. both device deselect and nop command can not affect oper- ation already in progress. so even if t he device is deselected or nop command is issued under operation, t he operation will be completed. a10/ap ba1 ba0 precharge 000 bank a only 001 bank b only 0 1 0 bank c only 0 1 1 bank d only 1 x x all banks figure 1. bank activation command cycle timing figure 2. burst read operation timing - 5 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 6. burst read operation burst read operation in mobile ddr sdram is in the same manner as the mobile sdr sdram such that the burst read command is issu ed by asserting cs and cas low while holding ras and we high at the rising edge of the clock(ck) after trcd from the bank activation. the address inputs determine the starting address for the burst. the mode register sets type of burst (sequential or interleave) and burst length(2, 4, 8, 1 6). the first output data is available with a cas latency from the read command, and the c onsecutive data are presented on the falling and rising edge of da ta strobe (dqs) adopted by mobile ddr sdram until the burst length is completed. note : 1) burst length=4, cas latency= 3. command read a nop nop nop nop nop nop nop nop 2 01 5 34 8 67 dqs dqs dout 0 dout 1 dout 2 dout 3 t rpst t rpre preamble postamble ck ck t dqsck t ac hi-z hi-z figure 3. burst write operation timing - 6 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 7. burst write operation the burst write command is issued by having cs , cas , and we low while holding ras high at the rising edge of the clock (ck). the address inputs determine the starting column address. there is no write latency relative to dqs requi red for burst write cycle. the first data of a burst write cycle must be applied on the dq pins tds (data-in setup time) prior to data strobe edge enabled after tdqss from the rising edge of the clock (ck) that the write com- mand is issued. the remaining data inputs must be supplied on each subsequent falling and rising edge of data strobe until the burst length is completed. when the burst has been finished, any additional data supplied to t he dq pins will be ignored. note : 1) burst length=4. 2) the specific requirement is that dqs be valid (high or low) on or before this ck edge. the case shown (dqs going from high_z to logic low) applies when no writes were pr eviously in pr ogress on the bus. command twr twr t dqss(min) t dqss(max) 2 01 5 34 8 67 t wpres t wpreh t wpres t wpreh ck ck din 3 din 0 din 1 din 2 din 3 din 0 din 1 din 2 din 3 din 0 din 1 din 2 din 3 din 0 din 1 din 2 nop writea nop nop nop writeb nop nop nop t ds t dh hi-z hi-z hi-z hi-z tdqss(max) tdqss(min) dqs dqs dqs dqs figure 4. read interrupted by a read timing figure 5. read interrupted by a write and burst stop timing - 7 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 8. read interrupted by a read a burst read can be interrupted by new read command of any bank befor e completion of the burst. when the previous burst is inte rrupted, the new address with the full burst length override the remaining address. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command is satisfied. at this point, the data from the interrupting read command appears. re ad to read interval is minimum 1 clock. note : 1) burst length=4, cas latency=3 9. read interrupted by a write & burst stop to interrupt a burst read with a write command, burst stop command must be asserted to avoid data contention on the i/o bus by placing the dqs (output drivers) in a high impedance state. note : 1) burst length=4, cas latency=3 . the following functionality establishes how a write command may interrupt a burst read. 1. for write commands interrupting a burst read, a burst terminate command is required to stop the burst read and tri-state the dq bus prior to valid input write data. burst stop command must be applied at least 2 cloc k cycles for cl=2 and at leas t 3 clock cycles for cl=3 before the write command. 2. it is illegal for a write command to interrupt a read with autoprecharge command. command read read nop nop nop nop nop nop nop dqs dqs dout a 0 dout a 1 dout b 0 dout b 1 dout b 2 dout b 3 ck 2 01 5 34 8 67 t rpre preamble t dqsck ck ck ck t ccd(min) t rpst hi-z hi-z command read burst stop nop write nop nop nop dqs dqs dout 0 dout 1 din 0 din 1 din 2 din 3 2 01 5 34 8 67 nop t wpreh t wpres t rpre t dqss t dqsck t ac ck ck nop t wpst hi-z hi-z t wpre t rpst figure 6. read interrupted by a precharge timing - 8 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 10. read interrupted by a precharge a burst read operation can be interrupted by precharge of the same bank. the minimum 1 clock is required for the read to precha rge intervals. the latency from a precharge command to invalid output is equivalent to the cas latency. note : 1) burst length=8, cas latency=3 . when a burst read command is issued to a mobile ddr sdram, a prec harge command may be issued to the same bank before the read b urst is completed. the following functionality determines when a precharge command may be given during a read burst and when a new bank activate command may be issued to the same bank. 1. for the earliest possible precharge comm and without interrupting a burst read, the precharge command may be given on the ris ing clock edge which is cl clock cycles before the end of the read burst where cl is the cas latency. a new bank activate command may be issued to t he same bank after trp (row precharge time). 2. when a precharge command interrupts a burst read operation, the precharge command given on a rising clock edge terminates th e burst with the last valid data word presented on dq pins at cl-1(cl=cas latency) cl ock cycles after the command has been issued. once the last data word has been output, the output buffers are tri-stated. a new bank activate command may be issued to the same bank after trp. 3. for a read with autoprecharge command, a new bank activate command may be issued to the same bank after trp from rising cloc k that comes cl(cl=cas latency) clock cy cles before the end of the read burst. during read with autoprecharge, the initiation of the interna l precharge occurs at the same time as the earliest possible exte rnal precharge command would initiate a precharge operation without interrupting the rea d burst as described in 1 above. 4. for all cases above, trp is an analog delay that needs to be c onverted into clock c ycles. the number of clock cycles between a precharge command and a new bank activate command to the same bank equals trp/tck (where tck is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. (note that rounding to x.5 is not poss ible since the precharge and bank activate commands can only be g iven on a rising clock edge).in all cases, a precharge operation cannot be initiated unless tras(min) [minimum bank activate to precharge time] has be en satisfied. this includes read with autoprecharge commands where tras(min) must still be satisfied such that a read with autoprecharge command h as the same timing as a read command followed by the earliest possible precharge command which does not interrupt the burst. command read nop precharge nop nop nop nop nop nop dqs dqs dout 0 dout 1 dout 2 dout 3 interrupted by precharge 2 01 5 34 8 67 dout 4 dout 5 dout 6 dout 7 1tck t rpre t dqsck t ac ck ck hi-z hi-z figure 7. write interrupted by a write timing - 9 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 11. write interrupted by a write a burst write can be interrupted by a new write command before completion of the burst, where the interval between the successi ve write commands must be at least one clock cycle(tccd(min)). when the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. note : 1) burst length=4. command nop write a write b nop nop nop nop nop nop dqs dqs din a 0 din a 1 din b 0 din b 1 din b 2 din b 3 tccd(min) 2 01 5 34 8 67 ck ck hi-z hi-z figure 8. write interrupted by a precharge and dm timing - 10 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 12. write interrupted by a precharge & dm a burst write operation can be interrupted by a precharge of the same bank before completion of the burst. random column access is allowed. a write recovery time(twr) is required from the last data to precharge command. when precharge command is asserted, any residual data f rom the burst write cycle must be masked by dm. note : 1) burst length=8. precharge timing for write operations in mobile ddr sdram requires enough time to allow ?write recovery? which is the time requ ired by a mobile ddr sdram core to properly store a full ?0? or ?1? level before a precharge operation. for mobile ddr sdram, a timing parameter, tw r, is used to indicate the required amount of time between the last valid write operation and a precharge command to the same bank. the precharge timing for writes is a comple x definition since the write data is sampled by the data strobe and the address is s ampled by the input clock. inside the mobile ddr sdram, the data path is eventually synchronized wi th the address path by switching clock domains from the data strobe clock domain to the input clock domain. this makes the definition of when a precharge operation can be initiated after a write very c omplex since the write recovery parameter must make reference to only the clock domain that affects internal write operation, i.e., the input clock do main. twr starts on the rising clock edge after the last possible dqs edge that strobed in the last valid data and ends on the rising clock edge that strobes in the precharge command. 1. for the earliest possible precharge command following a burst write without interrupting the burst, the minimum time for wri te recovery is defined by twr. 2. when a precharge command interrupts a write burst operation, the data mask pin, dm, is used to mask input data during the ti me between the last valid write data and the rising clock edge on wh ich the precharge command is given. duri ng this time, the dqs input is still re quired to strobe in the state of dm. the minimum time for write recovery is defined by twr. 3. for a write with autoprecharge command, a new bank activate co mmand may be issued to the same bank after twr+trp where twr+t rp starts on the falling dqs edge that strobed in the last valid data and e nds on the rising clock edge that strobes in the bank activate co mmand. during write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external precharg e command without interrupting the write burst as described in 1 above. 4. in all cases, a precharge operation cannot be initiated unless tras(min) [minimum bank activa te to precharge time] has been satisfied. this includes write with autoprecharge commands where tras(min) must still be satisfied such that a write with autoprecharge command has the same timing as a write command followed by the earliest possible precharge command which does not interrupt the burst. dina 2 dina 3 command nop write a nop nop prechargea nop nop write b dqs dqs dina 0 dina 1 dina 4 dina 5 dinb 0 dinb 1 dina 6 dina 7 twr dqs dqs twr t dqss(min) dina 0 dina 1 dina 2 dina 3 dina 4 dina 5 dina 6 dina 7 dm dinb 0 dinb 1 t dqss(max) 2 01 5 34 8 67 dm t wpres twpreh t wpres t wpreh nop t dqss(max) t wpres twpreh t dqss(min) t wpres t wpreh dinb 2 ck ck tdqss(max) tdqss(min) hi-z hi-z hi-z hi-z figure 9. write interrupted by a read and dm timing - 11 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 13. write interrupted by a read & dm a burst write can be interrupted by a read command of any bank. t he dq?s must be in the high impedance state at least one clock cycle before the inter- rupting read data appear on the outputs to avoid data contention. when the read command is registered, any residual data from t he burst write cycle must be masked by dm. the delay from the last data to read command (tcdl r) is required to avoid the da ta contention mobile ddr sdram inside. data that are presented on the dq pins before the read command is initia ted will actually be written to the memory. read command interrupting write can not be issued at the next clock edge of that of write command. note : 1) burst length=8, cas latency=3 . the following function establis hed how a read command may interrupt a write burst and which input data is not written into the memory. 1. for read commands interrupting a burst write, the minimum writ e to read command delay is 2 clock cycles. the case where the write to read delay is 1 clock cycle is disallowed. 2. for read commands interrupting a burst write, the dm pin mu st be used to mask the input data words which immediately precede the interrupting read operation and the input data word which immediately follows the interrupting read operation 3. for all cases of a read interrupting a write, the dq and dqs bus es must be released by the driving chip (i.e., the memory co ntroller) in time to allow the buses to turn around before the mobile d dr sdram drives them during a read operation. 4. if input write data is masked by the read command, the dqs input is ignored by the mobile ddr sdram. 5. refer to burst write operation. command nop write nop nop read nop nop nop nop din 0 din 1 din 2 din 3 din 4 din 5 din 6 din 7 tcdlr tdqss(max) tcdlr tdqss(min) din 7 din 0 din 1 din 2 din 3 din 4 din 5 din 6 2 0 1 5 3 4 8 6 7 twpres ck ck dqs dqs dqs dqs dm dm tdqss(max) tdqss(min) nop dout0 dout1 dout2 dout3 hi-z hi-z hi-z hi-z dout0 dout1 dout2 dout3 9 dout4 dout4 nop twpres figure 10. burst stop timing - 12 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 14. burst stop the burst stop command is initiated by having ras and cas high with cs and we low at the rising edge of the clock(ck). the burst stop command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has been complete d. when the burst stop command is issued during a burst read cycle, the pair of data and dqs(data strobe) go to a high impedance state after a delay w hich is equal to the cas latency set in the mode register. however, the burst stop command is not supported during a burst write operation. note : 1) burst length=4, cas latency= 3. the burst stop command is a mandatory feature for mobi le ddr sdram. the following functionality is required: 1. the burst stop command may only be issued on the rising edge of the input clock, ck. 2. burst stop is only a valid command during read bursts. 3. burst stop during a write burst is undefined and shall not be used. 4. burst stop applies to all burst lengths. 5. burst stop is an undefined command during read with autoprecharge and shall not be used. 6. when terminating a burst read command, the bst command must be issued l bst (?bst latency?) clock cy cles before the clock edge at which the output buffers are tristated, where l bst equals the cas latency for read operations. 7. when the burst terminates, the dq and dqs pins are tristated. the burst stop command is not byte controllable and applies to all bits in the dq data word and the(all) dqs pin(s). command read a burst stop nop nop nop nop nop nop nop dqs dqs dout 0 dout 1 2 01 5 34 8 67 the burst read ends after a delay equal to the cas latency. ck ck hi-z hi-z figure 11. dm masking timing - 13 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 15. dm masking the mobile ddr sdram has a data mask function that can be used in conjunction with data write cycle, not read cycle. when the d ata mask is acti- vated(dm high) during write operation, mobile ddr sdram does not accept the corresponding data.(dm to data-mask latency is zero ). dm must be issued at the rising or falling edge of data strobe. note : 1) burst length=8. command write nop nop nop nop nop nop nop nop dqs dqs din 0 din 1 din 2 din 3 dm din 4 din 5 din 6 din7 masked by dm=h 2 01 5 34 8 67 t dqss t wpres t wpreh ck ck hi-z hi-z figure 12. read with auto precharge timing - 14 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 16. read with auto precharge if a10/ap is high when read command is issued, the read with auto-p recharge function is performed. if a read with auto-precharg e command is issued, the mobile ddr sdram automatically enters the precharge operation bl/2 clock later from a read with auto-precharge command when tras(min) is sat- isfied. if not, the start point of precharge operation will be delayed until tras(min) is satisfi ed. once the precharge operati on has started, the bank cannot be reactivated and the new command can not be assert ed until the precharge time(trp) has been satisfied. note : 1) burst length=4, cas latency= 3. 2) the row active command of the precharge ba nk can be issued after trp from this point. note : 1) ap = auto precharge. asserted command for same bank for different bank 5 6 7 5 6 7 read read +no ap 1) read+no ap illegal legal legal legal read+ap read + ap read + ap illegal legal legal legal active illegal illegal illegal legal legal legal precharge legal legal illegal legal legal legal command bank a nop read a nop nop nop nop active auto precharge dqs dqs dout0 dout1 dout2 dout3 nop t rp bank can be reactivated at nop nop nop nop tras(min) auto-precharge starts ck ck completion of trp 2) hi-z hi-z 2 01 5 34 8 67 91011 figure 13. write with auto precharge timing - 15 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 17. write with auto precharge if a10/ap is high when write command is issued, the write with auto-precharge function is performed. any new command to the sam e bank should not be issued until the internal precharge is completed. th e internal precharge begins after keeping twr(min). note : 1) burst length=4. 2) the row active command of the precharge ba nk can be issued after trp from this point. note : 1) ap = auto precharge. 2) dm : refer to "27. write interrupted by precharge & dm ". asserted command for same bank for different bank 5 6 7 8 9 10 5 6 7 8 9 write write+ no ap 1) write+ no ap illegal illegal illegal illegal legal legal legal legal legal write+ ap write+ ap write+ ap illegal illegal illegal illegal legal legal legal legal legal read illegal read+ no ap+dm 2) read+ no ap+dm read+ no ap illegal illegal illegal illegal illegal legal legal read+ap illegal read + ap+dm read + ap+dm read + ap illegal illegal illegal illegal illegal legal legal active illegal illegal illegal ill egal illegal illegal legal legal legal legal legal precharge illegal illegal illegal il legal illegal illegal legal legal legal legal legal command bank a nop write a nop nop nop nop active auto precharge 2 01 5 34 8 67 dqs dqs din 0 din 1 din 2 din 3 nop t rp nop nop nop 91011 t wr internal precharge start ck ck bank can be reactivated at completion of t rp 2) hi-z hi-z nop nop nop 12 13 - 16 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 18. auto refresh & self refresh figure 14. auto refresh timing figure 15. self refresh timing 18.1. auto refresh an auto refresh command is issued by having cs , ras and cas held low with cke and we high at the rising edge of the clock(ck). all banks must be precharged and idle for trp(min) before the auto refresh command is applied. once this cycle has been started, no control of th e external address pins are required because of the internal address counter. when the refres h cycle has completed, all banks will be in the idle state . a delay between the auto refresh command and the next activate command or subsequent auto re fresh command must be greater than or equal to the trfc(min) . note : 1) trp=3clk 2) device must be in the all banks idle state prior to entering auto refresh mode. 18.2. self refresh a self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. once the self refresh com- mand is initiated, cke must be held low to keep the device in se lf refresh mode. after 1 clock cyc le from the self refresh comm and, all of the external control signals including system clock(ck, ck ) can be disabled except cke. the clock is internally di sabled during self refresh operation to reduce power. before returning cke high to exit the self refresh mode , apply stable clock input signal with deselect or nop command as serted. note : 1) device must be in the all banks idle state prior to entering self refresh mode. 2) the minimum time that the device must remain in self refresh mode is trfc. command cke pre t rp t rfc(min) auto = high refresh nop figure 16. power down entry and exit timing - 17 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 19. power down the device enters power down mode when cke low, and it exits when cke high. once the power down mode is initiated, all of the r eceiver circuits except ck and cke are gated off to reduce power consumption. all banks should be in idle state prior to entering the precharge power down mode and cke should be set in high for at least tpdex prior to row acti ve command. refresh operations cannot be performed during power d own mode, therefore the device cannot remain in power down mode longer than the refresh period(tref) of the device. note : 1) device must be in the all banks idle state prior to entering power down mode. 2) the minimum power down duration is specified by tcke. high-z cke precharge active power entry down precharge command t is t is t is t is figure 17. clock stop mode entry and exit - 18 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 20. clock stop stopping a clock during idle periods is an ef fective method of reducing power consumption. the lpddr sdram supports clock stop under the following conditions : - the last command (active, read, write, precharge, auto refres h or mode register set) has executed to completion, including an y data-out during read bursts; the number of clock pulses per ac cess command depends on the device?s ac timing parameters and the clock frequency; - the related timing conditions (trcd, twr, trp, trfc, tmrd) has been met; - cke is held high when all conditions have been met, the device is either in "idle state"or "row ac tive state" and clock stop mode may be entered with ck held low and ck held hight. clock stop mode is exited by restarting the clock. at least one nop command has to be issued before the next access command any be applied. addi- tional clock pulses might be required de pending on the system characteristics. figure shows clock stop mode entry and exit. - initially the device is in clock stop mode - the clock is restarted with the rising edge of t0 and a nop on the command inputs - with t1 a valid access command is latched; this command is followed by nop commands in order to allow for clock stop as soon as this access com- mand is completed. - tn is the last clock pulse requir ed by the access command latched with t1 - the clock can be stopped after tn. ck ck t0 t1 t2 tn cke timing condition command nop cmd nop nop nop address - 19 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 timing diagram figure 18. power up sequence for mobile ddr sdram - 20 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 1. power up sequence for mobile ddr sdram note : 1) apply power and attempt to maintain cke at a high state and all other inputs may be undefined. - apply vdd before or at the same time as vddq. 2) maintain stable power, stable clock and nop input condition for a minimum of 200us. 3) issue precharge commands for all banks of the devices. 4) issue 2 or more auto-refresh commands. 5) issue a mode register set command to initialize the mode register. figure 19. basic timing (setup, hold and access time @bl=4, cl=3) - 21 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 2. basic timing 0123456789101112131415 cke cs ras cas a10/ap addr dqs (a0~an) dqs : don?t care ck ck high baa dm command active t rpre read write baa bab ra ra ca cb db0 db1 db2 db3 qa0 qa1 qa2 qa3 t ac t wpres t dqss t dsc t dqsh t dqsl t wpst t rpst t ds t dh t ck t ch t cl t ck t ch t cl t is t ih ba0, ba1 t wpreh we t dqsck hi-z hi-z hi-z hi-z hi-z hi-z t qhs figure 20. multi bank interleaving read (@bl=4, cl=3) - 22 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 3. multi bank interleaving read 0123456789101112131415 cke cs ras cas ba0,ba1 a10/ap addr dqs (a0~an) dqs : don?t care ck ck high baa dm command qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 active t rrd t ccd bab baa bab ra ra rb ca cb active read read t rcd rb we hi-z hi-z figure 21. multi bank interleaving write (@bl=4) - 23 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 4. multi bank interleaving write 0123456789101112131415 cke cs ras cas ba0,ba1 a10/ap addr dqs (a0~an) dqs : don?t care ck ck high baa dm command da0 da1 da2 da3 db0 db1 db2 db3 active t rrd t ccd bab baa bab ra rb ca cb active write write t rcd we ra rb hi-z hi-z figure 22. read with auto precharge (@bl=8) - 24 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 5. read with auto precharge note : 1) the row active command of the precharge bank can be issued after trp from this point. 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high baa qa0 qa1 qa2 qa4 qa5 qa6 command read qa7 qa3 active ra ca ra (cl=3) (cl=3) auto precharge start t rp note 1) we baa hi-z hi-z figure 23. write with auto precharge (@bl=8) - 25 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 6. write with auto precharge note : 1) the row active command of the precharge bank can be issued after trp from this point 0123456789101112131415 auto precharge start cke cs ras cas ba0,ba1 a10/ap addr dqs (a0~an) dqs : don?t care ck ck high baa baa ra ca ra dm command da0 da1 da2 da3 da4 da5 da6 da7 write active note 1) t wr t rp we hi-z hi-z figure 24. write followed by precharge (@bl=4) - 26 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 7. write followed by precharge 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high da0 da1 da2 da3 command write baa ca pre charge t wr baa we hi-z hi-z figure 25. write interrupted by precharge & dm (@bl=8) - 27 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 8. write interrupted by precharge & dm 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high baa da0 da1 da2 da3 da4 da6 da7 command write da5 t wr bab bac baa ca cb cc db0 db1 dc0 dc2 dc3 dc1 t ccd pre charge write write we dc 4 5 11 12 6 7 1 figure 26. write interrupted by a read (@bl=8, cl=3) - 28 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 9. write interrupted by a read 0123456789 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high da0 da1 da2 da3 da4 da5 command write bab ca cb qb0 qb1 qb2 qb3 read t cdlr masked by dm baa we qb 4 5 6 7 figure 27. read interrupted by precharge (@bl=8, cl=3) - 29 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 10. read interrupted by precharge 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high qa0 qa1 qa2 qa3 qa4 command read baa qa5 pre baa ca charge 2 t ck valid we hi-z hi-z figure 28. read interrupted by a write & burst stop (@bl=8, cl=3) - 30 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 11. read interrupted by a write & burst stop 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high qa0 qa1 qb0 qb1 qb2 qb4 qb5 qb6 command read baa qb7 qb3 burst bab ca cb write stop we 11 hi-z hi-z figure 29. read interrupted by a read (@bl=8, cl=3) - 31 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 12. read interrupted by a read 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high baa qa0 qa1 qb0 qb1 qb2 qb4 qb5 qb6 command read bab ca cb qb7 qb3 read we hi-z hi-z figure 30. dm function (@bl=8) only for write - 32 - K522H1HACF-B050 datasheet mcp memory rev. 1.0 13. dm function 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high baa ca da0 da1 da2 da3 da5 da6 da7 command write da4 we hi-z hi-z |
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